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1 ? fn3142.5 HI-506, hi-507, hi-508, hi-509 single 16 and 8/differen tial 8-channel and 4-channel cmos analog multiplexers the HI-506/hi-507 and hi-508/hi-509 monolithic cmos multiplexers each include an array of sixteen and eight analog switches respectively, a digital decoder circuit for channel selection, voltage reference for logic thresholds, and an enable input for device selection when several multiplexers are present. the dielectric isolation (di) process used in fabrication of these devices eliminates the problem of latchup. di also offers much lower substrate leakage and parasitic capacitance than conventional junction isolated cmos (see application notes an520 and an521). the switching threshold for each digital input is established by an internal +5v reference, providing a guaranteed minimum 2.4v for logic ?1? and maximum 0.8v for logic ?0?. this allows direct interface without pullup re sistors to signals from most logic families: cmos, ttl, dtl and some pmos. for protection against transient overvoltage, the digital inputs include a series 200 ? resistor and diode clamp to each supply. the HI-506 is a single 16-channel, the hi-507 is an 8-channel differential, the hi-508 is a single 8-channel and the hi-509 is a 4-channel differential multiplexer. if input overvoltages are pres ent, the hi-546/ hi-547/hi-548/ hi-549 multiplexers are recommended. features ? low on resistance . . . . . . . . . . . . . . . . . . . . . . . . 180 ? ? wide analog signal range . . . . . . . . . . . . . . . . . . . . . 15v ? ttl/cmos compatible ? access time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns ? maximum power supply . . . . . . . . . . . . . . . . . . . . . . 44v ? break-before-make switching ? no latch-up ? replaces dg506a/dg506aa and dg507a/dg507aa ? replaces dg508a/dg508aa and dg509a/dg509aa applications ? data acquisition systems ? precision in strumentation ? demultiplexing ? selector switch ordering information part number temp. range ( o c) package pkg. dwg. # hi1-0506-2 -55 to 125 28 ld cerdip f28.6 hi1-0506-5 0 to 75 28 ld cerdip f28.6 hi3-0506-5 0 to 75 28 ld pdip e28.6 hi4p0506-5 0 to 75 28 ld plcc n28.45 hi9p0506-9 -40 to 85 28 ld soic m28.3 hi1-0507-2 -55 to 125 28 ld cerdip f28.6 hi3-0507-5 0 to 75 28 ld pdip e28.6 hi1-0508-2 -55 to 125 16 ld cerdip f16.3 hi1-0508-5 0 to 75 16 ld cerdip f16.3 hi3-0508-5 0 to 75 16 ld pdip e16.3 hi9p0508-5 0 to 75 16 ld soic m16.15 hi9p0508-9 -40 to 85 16 ld soic m16.15 hi1-0509-2 -55 to 125 16 ld cerdip f16.3 hi1-0509-4 -25 to 85 16 ld cerdip f16.3 hi1-0509-5 0 to 75 16 ld cerdip f16.3 hi3-0509-5 0 to 75 16 ld pdip e16.3 hi4p0509-5 0 to 75 20 ld plcc n20.35 hi9p0509-5 0 to 75 16 ld soic m16.15 data sheet august 2003 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 pinouts HI-506 (pdip, cerdip, soic) top view hi-507 (pdip, cerdip) top view HI-506 (plcc) top view +v supply nc nc in 16 in 15 in 14 in 13 in 12 in 11 in 10 in 9 gnd nc address a 3 out in 8 in 7 in 6 in 5 in 3 in 1 enable address a 0 address a 1 address a 2 -v supply in 4 in 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 +v supply out b nc in 8b in 7b in 6b in 5b in 4b in 3b in 2b in 1b gnd nc nc out a in 8a in 7a in 6a in 5a in 3a in 1a enable address a 0 address a 1 address a 2 -v supply in 4a in 2a 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 in 15 in 14 in 13 in 12 in 11 in 10 in 9 in 16 nc nc +v supply out -v supply in 8 gnd nc a 3 a 2 a 1 enable a 0 in 7 in 6 in 5 in 4 in 3 in 2 in 1 11 10 5 6 7 8 9 23 24 25 22 21 20 19 14 15 16 17 18 12 13 321 4282726 HI-506, hi-507, hi-508, hi-509
3 hi-508 (pdip, cerdip, soic) top view hi-509 (pdip, cerdip, soic) top view hi-509 (plcc) top view pinouts (continued) 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 a 0 enable -v supply in 1 in 2 in 3 out in 4 a 1 gnd +v supply in 5 in 6 in 7 in 8 a 2 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 a 0 enable -v supply in 1a in 2a in 3a out a in 4a a 1 +v supply in 1b in 2b in 3b in 4b out b gnd -v supply in 1a nc in 2a in 3a enable a 0 nc a 1 gnd in 4a out a nc out b in 4b +v supply in 1b nc in 2b in 3b 4 5 6 7 8 10 11 12 13 9 3212019 16 17 18 15 14 HI-506, hi-507, hi-508, hi-509
4 truth tables HI-506 a 3 a 2 a 1 a 0 en ?on? channel xxxxl none llllh 1 lllhh 2 llhlh 3 l lhhh 4 lhllh 5 lhlhh 6 lhhlh 7 lhhhh 8 hlllh 9 hllhh 10 hlhlh 11 hlhhh 12 hhl lh 13 hhlhh 14 hhhlh 15 hhhhh 16 hi-507 a 2 a 1 a 0 en ?on? channel x x x l none lllh 1 llhh 2 lhlh 3 lhhh 4 hllh 5 hlhh 6 hhlh 7 hhhh 8 hi-508 a 2 a 1 a 0 en ?on? channel x x x l none lllh 1 llhh 2 lhlh 3 lhhh 4 hllh 5 hlhh 6 hhlh 7 hhhh 8 hi-509 a 1 a 0 en ?on? channel pair x x l none llh 1 lhh 2 hlh 3 hhh 4 HI-506, hi-507, hi-508, hi-509
5 functional diagrams HI-506 hi-507 hi-508 hi-509 decoder/ driver ? ? ? ? out in 1 in 2 in 16 ? digital protection a 0 a 1 a 2 a 3 ? en input level shift 5v ref decoder/ driver ? ? ? out b in 8a in 1a in 1b ? digital protection a 0 a 1 a 2 ? en input level shift 5v ref out a in 8b decoder/ driver ? ? ? out in 1 in 2 in 8 ? digital protection a 0 a 1 a 2 ? en input level shift 5v ref decoder/ driver ? ? out b in 4a in 1a in 1b ? digital protection a 0 a 1 ? en input level shift 5v ref out a in 4b HI-506, hi-507, hi-508, hi-509
6 schematic diagrams address decoder address input buffer level shifter ttl reference circuit multiplex switch p n a 0 or a 0 to n-channel device of the switch a 1 or a 1 a 2 or a 2 a 3 or a 3 enable pp pp p p v+ v- n n n n nn to p-channel device of the switch delete a 3 or a 3 input for hi-507, hi-508, hi-509 delete a 2 or a 2 input for hi-509 v+ p3 d1 d2 200 ? a in v r all n-channel bodies to v- all p-channel bodies to v+ unless otherwise indicated a v- p1 n1 v l p2 n2 n3 v- v+ p4 p5 p6 p7 p8 p9 p10 n6 n7 n8 n9 n10 n4 n5 a v l q9p q10n n13 n14 p15 q1p n15 q5n d3 q11p r3 6.8k p16 r2 16.8k q12n q6n q2p v+ q3p q4p n12 q7p v- gnd q8n v r from decode v+ n18 n19 p17 n17 v- p18 out from decode in HI-506, hi-507, hi-508, hi-509
7 absolute maximum rati ngs thermal information v+ to v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44v v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+22v v- to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25v digital input voltage (v en , v a ) . . . . . (v-) -4v to (v+) +4v or 20ma, whichever occurs first analog signal (v in , v out , note 2) . . . . . . . . . . (v-) -2v to (v+) +2v continuous current, in or out . . . . . . . . . . . . . . . . . . . . . . . . . 20ma peak current, in or out (pulsed 1ms, 10% duty cycle max) . 40ma operating conditions temperature ranges HI-506/507/508/509-2 . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c HI-506/508/509-4 . . . . . . . . . . . . . . . . . . . . . . . . . . -25 o c to 85 o c HI-506/507/508/509-5 . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 75 o c HI-506/508-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c typical minimum supply voltage. . . . . . . . . . . . 10v or single 20v thermal resistance (typical, note 1) ja ( o c/w) jc ( o c/w) 16 ld cerdip package. . . . . . . . . . . . 85 32 16 ld soic package . . . . . . . . . . . . . . 115 n/a 16 ld pdip package . . . . . . . . . . . . . . 100 n/a 20 ld plcc package. . . . . . . . . . . . . . 80 n/a 28 ld cerdip package. . . . . . . . . . . . 55 18 28 ld pdip package . . . . . . . . . . . . . . 60 n/a 28 ld soic package . . . . . . . . . . . . . . 70 n/a 28 ld plcc package. . . . . . . . . . . . . . 70 n/a maximum junction temperature ceramic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 o c plastic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic and plcc - lead tips only) caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on a low effective ther mal conductivity test board in free air. see tech brief tb379 fo r details. 2. signals on in or out exceeding v+ or v- ar e clamped by internal diodes. limit result ing current to maximum current ratings. i f an overvoltage condition is anticipated (analog input exc eeds either power supply voltage), the intersil hi-546/hi-547/hi-548/hi-549 multiplex ers are recommended. electrical specifications supplies = +15v, -15v; v ah (logic level high) = 2.4v; v al (logic level low) = 0.8v, unless otherwise specified. for test c onditions, consult test circuits section parameter test conditions temp ( o c) -2 -4, -5, -9 units min typ max min typ max dynamic characteristics access time, t a 25 - 250 500 - 250 - ns full - - 1000 - - 1000 ns break-before-make delay, t open 25 25 80 - 25 80 - ns enable delay (on), t on(en) 25 - 250 500 - 250 - ns full - - 1000 - - 1000 ns enable delay (off), t off(en) 25 - 250 500 - 250 - ns full - - 1000 - - 1000 ns settling time, t s (HI-506 and hi-507) to 0.1% 25 - 1.2 - - 1.2 - s to 0.01% 25 - 2.4 - - 2.4 - s settling time, t s (hi-508 and hi-509) to 0.1% 25 - 360 - - 360 - ns to 0.01% 25 - 600 - - 600 - ns off isolation note 6 25 50 68 - 50 68 - db channel input capacitance, c s(off) 25 -10- -10-pf channel output capacitance, c d(off) HI-506 25 -52- -52-pf hi-507 25 -30- -30-pf hi-508 25 -17- -17-pf hi-509 25 -12- -12-pf digital input capacitance, c a 25 - 6 - - 6 - pf input to output capacitance, c ds(off) 25 - 0.08 - - 0.08 - pf digital input characteristics input low threshold, v al full - - 0.8 - - 0.8 v input high threshold, v ah full 2.4 - - 2.4 - - v input leakage current (high or low), i a note 5 full - - 1.0 - - 1.0 a HI-506, hi-507, hi-508, hi-509
8 analog channel characteristics analog signal range, v in full -15 - +15 -15 - +15 v on resistance, r on note 3 25 - 180 300 - 180 400 ? ? r on , (any two channels) 25 - 5 - - 5 - % off input leakage current, i s(off) note 4 25 - 0.03 - - 0.03 - na full - - 50 - - 50 na off output leakage current, i d(off ) note 4 25 - 0.3 - - 0.3 - na HI-506 full - - 300 - - 300 na hi-507 full - - 200 - - 200 na hi-508 full - - 200 - - 200 na hi-509 full - - 100 - - 100 na on channel leakage current, i d(on) note 4 25 - 0.3 - - 0.3 - na HI-506 full - - 300 - - 300 na hi-507 full - - 200 - - 200 na hi-508 full - - 200 - - 200 na hi-509 full - - 100 - - 100 na differential off output leakage current, i diff (hi-507, hi-509 only) full - - 50 - - 50 na power supply characteristics current, i+ HI-506/hi-507 note 7 full - 1.5 3.0 - 1.5 3.0 ma hi-508/hi-509 note 7 full - 1.5 2.4 - 1.5 2.4 ma current, i- HI-506/hi-507 note 7 full - 0.4 1.0 - 0.4 1.0 ma hi-508/hi-509 note 7 full - 0.4 1.0 - 0.4 1.0 ma power dissipation, p d HI-506/hi-507 full - - 60 - - 60 mw hi-508/hi-509 full - - 51 - - 51 mw notes: 3. v out = 10v, i out = + 1ma. 4. 10na is the practical lower limit for high s peed measurement in the production test environment. 5. digital input leakage is primarily due to the clamp diodes (see schematic). ty pical leakage is less than 1na at 25 o c. 6. v en = 0.8v, r l = 1k, c l = 15pf, v s = 7v rms , f = 100khz. 7. v en , v a = 0v or 2.4v. electrical specifications supplies = +15v, -15v; v ah (logic level high) = 2.4v; v al (logic level low) = 0.8v, unless otherwise specified. for test c onditions, consult test circuits section (continued) parameter test conditions temp ( o c) -2 -4, -5, -9 units min typ max min typ max test circuits and waveforms t a = 25 o c, v supply = 15v, v ah = 2.4v, v al = 0.8v, unless otherwise specified figure 1a. test circuit 1ma out in v in r on = v 2 1ma v 2 HI-506, hi-507, hi-508, hi-509
9 figure 1b. on resistance vs analog input voltage figure 1c. normalized on resistance vs supply voltage figure 1. on resistance figure 2a. leakage current vs temperature figure 2b. i d(off) test circuit (note 8) figure 2c. i s(off) test circuit (note 8) figure 2d. i d(on) test circuit (note 8) figure 2. leakage currents note: 8. two measurements per channel: 10v and + 10v. (two measurements per device for i d(off) 10v and + 10v) test circuits and waveforms t a = 25 o c, v supply = 15v, v ah = 2.4v, v al = 0.8v, unless otherwise specified (continued) 400 300 200 100 0 -15 analog input (v) on resistance ( ? ) -10 -5 0 5 10 15 125 o c 25 o c -55 o c 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 normalized resistance (referred to value at 15v) 10 11 12 13 14 15 supply voltage ( v) -55 o c to 125 o c v in = 0v 100 n a 10na 1na 100pa 10pa leakage current 25 50 75 100 125 temperature ( o c) off output leakage current i d(off) i d(on) off input leakage current i s(off) a + 10v 10v 0.8v en out i d(off) + 10v 10v 0.8v en a out i s(off) out i d(on) a + 10v 10v 2.4v en a 0 a 1 HI-506, hi-507, hi-508, hi-509
10 figure 3a. on channel current vs voltage figure 3b. test circuit figure 3. on channel current figure 4a. supply current vs toggle frequency figure 4b. test circuit figure 4. dynamic supply current test circuits and waveforms t a = 25 o c, v supply = 15v, v ah = 2.4v, v al = 0.8v, unless otherwise specified (continued) 70 60 50 40 30 20 10 0 024 6810121416 voltage across switch ( v) switch current (ma) -55 o c 25 o c 125 o c a v in 8 6 4 2 0 1k toggle frequency (hz) supply current (ma) 10k 100k 1m 10m v supply = 15v v supply = 10v 10v/ 5v +15v/+10v v+ v- in 1 in 2 in 8/16 out a 0 en a 1 10 14 m ? pf a 3 a 2 50 ? v a 3.5v gnd a -15v/-10v a -i supply +i supply + 10v/ + 5v v a high = 3.5v low = 0v 50% duty cycle thru in 7/15 HI-506 ? ? similar connection for hi-507/ hi-508/hi-509 HI-506, hi-507, hi-508, hi-509
11 figure 5a. access time vs logic level (high) figure 5b. test circuit figure 5c. measurement points figure 5d. waveforms figure 5. access time figure 6a. test circuit test circuits and waveforms t a = 25 o c, v supply = 15v, v ah = 2.4v, v al = 0.8v, unless otherwise specified (continued) 600 400 200 0 2 access time (ns) logic level (high) (v) 345 15 14 13 10v +15v v+ v- in 1 in 2 thru in 16 out a 0 en a 1 10 50 k ? pf a 3 a 2 50 ? v a 3.5v gnd -15v + 10v in 7/15 HI-506 ? ? similar connection for hi-507/ hi-508/hi-509 50% 3.5v 10% +10v 0v output -10v t a address drive (v a ) 200ns/div. s 1 on s 16 on v a input 2v/div. output 5v/div. +15v v+ v- in 1 in 2 thru in 8 /16 out a 0 en a 1 50pf 200 ? v out -15v a 3 a 2 50 ? v a 3.5v gnd +5v in 7/in 15 HI-506 ? ? similar connection for hi-507/hi-508/hi-509 HI-506, hi-507, hi-508, hi-509
12 figure 6b. measurement points figure 6c. waveforms figure 6. break-before-make delay figure 7a. test circuit figure 7b. measurement points figure 7c. waveforms figure 7. enable delays test circuits and waveforms t a = 25 o c, v supply = 15v, v ah = 2.4v, v al = 0.8v, unless otherwise specified (continued) 50% 50% 3.5v 0v output address drive (v a ) t open s 1 on s 16 on v a input 2v/div. output 1v/div. 100ns/div. +15v v+ v- in 1 in 2 thru in 8 /16 out a 0 en a 1 50pf 200 ? v out -15v a 3 a 2 v a gnd +10v in 7/in 15 HI-506 ? ? similar connection for hi-507/hi-508/hi-509 50 ? 3.5v 0v output t off(en) enable drive (v a ) 10% 50% 50% 90% t on(en) 0v disabled output 2v/div. enable drive 2v/div. enabled (s 1 on) 100ns/div HI-506, hi-507, hi-508, hi-509
13 typical performance curves t a = 25 o c, v supply = 15v, v ah = 2.4v, v al = 0.8v, unless otherwise specified figure 8. logic threshold vs power supply vo ltage figure 9. off isolation vs frequency figure 10a. HI-506/hi-507 figure 10b. hi-508/hi-509 figure 10. power supply current vs temperature 10 12 14 16 18 20 power supply voltage ( v) input logic threshold (v) 4 3 2 1 0 100 80 60 40 20 0 10 4 (v s ), (v d ) off isolation (db) 10 5 10 6 10 7 frequency (hz) v en = 0v c load = 28pf v s = 7v rms r l = 1k r l = 10m 3 2 1 0 power supply current (ma) -55 temperature ( o c) -35 -15 -5 45 25 65 85 105 125 v en = 2.4v v en = 0v 3 2 1 0 -55 power supply current (ma) temperature ( o c) -35 -15 -5 25 45 65 85 105 125 en = 5v en = 0v HI-506, hi-507, hi-508, hi-509
14 die characteristics die dimensions: 129 mils x 82 mils metallization: type: cual thickness: 16k ? 2k ? substrate potential (note): -v supply passivation: type: nitride/silox nitride thickness: 3.5k ? 1k ? silox thickness: 12k ? 2k ? worst case current density: 1.4 x 10 5 a/cm 2 transistor count: 421 process: cmos-di note: the substrate appears resistive to the -v supply terminal, therefore it may be left floating (insulating die mount) or it may be mounted on a conductor at -v supply potential. metallization mask layout HI-506 hi-507 +v in 16 in 15 in 14 in 13 in 12 in 11 in 10 in 9 gnd nc a 3 out in 8 in 7 in 6 in 5 in 3 in 1 en a 0 a 1 a 2 -v in 4 in 2 +v in 8b in 7b in 6b in 5b in 4b in 3b in 2b in 1b gnd out b nc out a in 8a in 7a in 6a in 5a in 3a in 1a en a 0 a 1 a 2 -v in 4a in 2a HI-506, hi-507, hi-508, hi-509
15 die characteristics die dimensions: 81.9 mils x 90.2 mils metallization: type: cual thickness: 16k ? 2k ? substrate potential (note): -v supply passivation: type: nitride/silox nitride thickness: 3.5k ? 1k ? silox thickness: 12k ? 2k ? worst case current density: 1.4 x 10 5 a/cm 2 transistor count: 234 process: cmos-di note: the substrate appears resistive to the -v supply terminal, therefore it may be left floating (insulating die mount) or it may be mounted on a conductor at -v supply potential. metallization mask layout hi-508 hi-509 +v sup gnd out in 8 in 7 in 6 in 5 in 3 in 1 en a 0 a 1 a 2 -v sup in 4 in 2 +v sup gnd out a in 4b in 3b in 2b in 1b in 3a in 1a en a 0 a 1 -v sup in 4a in 2a out b HI-506, hi-507, hi-508, hi-509
16 HI-506, hi-507, hi-508, hi-509 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the in ch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in je- dec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e16.3 (jedec ms-001-bb issue d) 16 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.735 0.775 18.66 19.68 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n16 169 rev. 0 12/93
17 HI-506, hi-507, hi-508, hi-509 dual-in-line plastic packages (pdip) notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the in ch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are m easured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shal l not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendic- ular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a1 -a- 0.010 (0.25) c a m bs e28.6 (jedec ms-011-ab issue b) 28 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.250 - 6.35 4 a1 0.015 - 0.39 - 4 a2 0.125 0.195 3.18 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.030 0.070 0.77 1.77 8 c 0.008 0.015 0.204 0.381 - d 1.380 1.565 35.1 39.7 5 d1 0.005 - 0.13 - 5 e 0.600 0.625 15.24 15.87 6 e1 0.485 0.580 12.32 14.73 5 e 0.100 bsc 2.54 bsc - e a 0.600 bsc 15.24 bsc 6 e b - 0.700 - 17.78 7 l 0.115 0.200 2.93 5.08 4 n28 289 rev. 1 12/00
18 HI-506, hi-507, hi-508, hi-509 ceramic dual-in-line fr it seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this co nfiguration dimension b3 replaces dimension b2. 5. this dimension allows for off- center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f16.3 mil-std-1835 gdip1-t16 (d-2, configuration a) 16 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.840 - 21.34 5 e 0.220 0.310 5.59 7.87 5 e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n16 168 rev. 0 4/94
19 HI-506, hi-507, hi-508, hi-509 ceramic dual-in-line fr it seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this co nfiguration dimension b3 replaces dimension b2. 5. this dimension allows for off- center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f28.6 mil-std-1835 gdip1-t28 (d-10, configuration a) 28 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.232 - 5.92 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 1.490 - 37.85 5 e 0.500 0.610 12.70 15.49 5 e 0.100 bsc 2.54 bsc - ea 0.600 bsc 15.24 bsc - ea/2 0.300 bsc 7.62 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n28 288 rev. 0 4/94
20 HI-506, hi-507, hi-508, hi-509 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m16.15 (jedec ms-012-ac issue c) 16 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3859 0.3937 9.80 10.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n16 167 0 o 8 o 0 o 8 o - rev. 0 12/93
21 HI-506, hi-507, hi-508, hi-509 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional . if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m28.3 (jedec ms-013-ae issue c ) 28 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.6969 0.7125 17.70 18.10 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n28 287 0 o 8 o 0 o 8 o - rev. 0 12/93
22 HI-506, hi-507, hi-508, hi-509 plastic leaded chip carrier packages (plcc) a1 a seating plane 0.020 (0.51) min view ?a? d2/e2 0.025 (0.64) 0.045 (1.14) r 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) tp e e1 0.042 (1.07) 0.048 (1.22) pin (1) identifier c l d1 d 0.020 (0.51) max 3 plcs 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) min 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) min view ?a? typ. 0.004 (0.10) c -c- d2/e2 c l notes: 1. controlling dimension: inch. conv erted millimeter dimensions are not necessarily exact. 2. dimensions and tolerancing per ansi y14.5m-1982. 3. dimensions d1 and e1 do not include mold protrusions. allowable mold protrusion is 0.010 inch (0.25mm) per side. dimensions d1 and e1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. to be measured at seating plane contact point. 5. centerline to be determined where center leads exit plastic body. 6. ?n? is the number of terminal positions. -c- n20.35 (jedec ms-018aa issue a) 20 lead plastic leaded chip carrier package symbol inches millimeters notes min max min max a 0.165 0.180 4.20 4.57 - a1 0.090 0.120 2.29 3.04 - d 0.385 0.395 9.78 10.03 - d1 0.350 0.356 8.89 9.04 3 d2 0.141 0.169 3.59 4.29 4, 5 e 0.385 0.395 9.78 10.03 - e1 0.350 0.356 8.89 9.04 3 e2 0.141 0.169 3.59 4.29 4, 5 n20 206 rev. 2 11/97
23 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com HI-506, hi-507, hi-508, hi-509 plastic leaded chip carrier packages (plcc) notes: 1. controlling dimension: inch. c onverted millimeter dimensions are not necessarily exact. 2. dimensions and tolerancing per ansi y14.5m-1982. 3. dimensions d1 and e1 do not include mold protrusions. allowable mold protrusion is 0.010 inch (0.25mm) per side. dimensions d1 and e1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. to be measured at seating plane contact point. 5. centerline to be determined where center leads exit plastic body. 6. ?n? is the number of terminal positions. -c- a1 a seating plane 0.020 (0.51) min view ?a? d2/e2 0.025 (0.64) 0.045 (1.14) r 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) tp e e1 0.042 (1.07) 0.048 (1.22) pin (1) identifier c l d1 d 0.020 (0.51) max 3 plcs 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) min 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) min view ?a? typ. 0.004 (0.10) c -c- d2/e2 c l n28.45 (jedec ms-018ab issue a) 28 lead plastic leaded chip carrier package symbol inches millimeters notes min max min max a 0.165 0.180 4.20 4.57 - a1 0.090 0.120 2.29 3.04 - d 0.485 0.495 12.32 12.57 - d1 0.450 0.456 11.43 11.58 3 d2 0.191 0.219 4.86 5.56 4, 5 e 0.485 0.495 12.32 12.57 - e1 0.450 0.456 11.43 11.58 3 e2 0.191 0.219 4.86 5.56 4, 5 n28 286 rev. 2 11/97

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